Development of Design Μethodologies and Cad Tools for System-level Evaluation of Interconnect Reliability Issues in Soc Designs Development of Design Μethodologies and Cad Tools for System-level Evaluation of Interconnect Reliability Issues in Soc Designs

The presented diploma thesis deals with interconnect reliability in VLSI systems from a system-level perspective. The dominant phenomena that are examined are Electromigration (EM) and Time-dependent Dielectric Breakdown (TDDB). The main goal of this work was the creation of a design flow that estimates the system’s lifetime (MTTF) because of timing failures caused by the gradual degradation of the electrical characteristics of interconnects. The presented flow is based on a pre-existing work that was developed at IMEC, Belgium. A main feature of the project is the use of actual temperature data for each individual region of the system, which are derived from application-specific simulations. This results in rather accurate lifetime estimations as both reliability-threatening phenomena examined are heavily dependent on temperature. Another improvement that increases the accuracy of the predictions is the estimation of the interconnets’ current density through Spice simulations. Other important features are the automation of the design flow as a tool as well as its compatibility with state-of-the-art EDA tools, such as the Cadence SoC Encounter Layout & Timing analysis system and the Synopsys front-end suite.